# ppc64 POWER5 events
#
#  Within each group the event names must be unique.  Each event in a group is
#  assigned to a unique counter.  The groups are from the groups defined in the
#  power5.evs and power5.gps files.
#
#  Only events within the same group can be selected simultaneously
#  Each event is given a unique event number.  The event number is used by the
#  Oprofile code to resolve event names for the postprocessing.  This is done to 
#  preserve compatibility with the rest of the Oprofile code.  The event
#  number must be between 0 and 255.

#Group Default
mmcr0:0x0400C000 mmcr1:0x4000000002341E36 mmcra:0x00000001 event:0002 counters:2 um:zero minimum:1000 name:CYCLES : Processor cycles

#Group 9 LSU SRQ and LMQ events
mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 event:0010 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GP9 : A TLB miss for a data request occurred 
mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 event:0011 counters:1 um:zero minimum:1000 name:PM_DC_PREF_L2_CLONE_L3_GP9 : L2 prefetch cloned with L3
mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 event:0012 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_LHR_MERGE_GP9 : Dcache miss occured for the same real cache line as earlier req, merged into LMQ
mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 event:0013 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GP9 : Cycles Store Req Queue empty
mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 event:0014 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_GP9 : Number of PPC inst completed
mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 event:0015 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_GP9 : Proc cycles gated by the run latch
 
#Group 13 Misc prefetch and reject events
mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 event:0020 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_SRQ_LHS_G13 : LSU0 reject due to load hit store
mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 event:0021 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_G13 : DL1 reloaded with modified data from L2 within this MCM
mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 event:0022 counters:2 um:zero minimum:1000 name:PM_DC_PREF_L2_CLONE_L3_G13 : L2 prefetch cloned with L3
mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 event:0023 counters:3 um:zero minimum:1000 name:PM_L2_PREF_G13 : L2 cacahe prefetchs
mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 event:0024 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G13 : Number of PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 event:0025 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G13 : Processor cycles gated by run latch

#Group 14 LSU reject events
mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 event:0030 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_G14 : Data loaded from l3.5 modified
mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 event:0031 counters:1 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_G14 : Cycles MSR (EE) bit off and external interupt pending 
mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 event:0032 counters:2 um:zero minimum:1000 name:PM_FLUSH_IMBAL_G14 : Flush caused by thread GCT imbalance
mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 event:0033 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_G14 : Marked SRQ flushes
mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 event:0034 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G14 : Instructions completed
mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 event:0035 counters:5 um:zero minimum:1000 name:PM_RUN_CYCLES_G14 : Processor cycles gated by run latch

#Group 25 LSU0/1 flush due to unaligned load
mmcr0:0x0400C000 mmcr1:0x40C0000080888A02 mmcra:0x00000001 event:0040 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_G25 : LSU0 unaligned load flush
mmcr0:0x0400C000 mmcr1:0x40C0000080888A02 mmcra:0x00000001 event:0041 counters:1 um:zero minimum:1000 name:PM_BR_MPRED_TA_G25 : Branch mispredictions due to taget address
mmcr0:0x0400C000 mmcr1:0x40C0000080888A02 mmcra:0x00000001 event:0042 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_G25 : Flush initiated by LSU
mmcr0:0x0400C000 mmcr1:0x40C0000080888A02 mmcra:0x00000001 event:0043 counters:3 um:zero minimum:1000 name:PM_INST_CMPL_G25 : Eligible Instructions completed
mmcr0:0x0400C000 mmcr1:0x40C0000080888A02 mmcra:0x00000001 event:0044 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G25 : Number of PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x40C0000080888A02 mmcra:0x00000001 event:0045 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G25 : Processor Cycles gated by run latch

#Group 26 LSU0/1 flush due to unaligned store
mmcr0:0x0400C000 mmcr1:0x40C00000828A028A mmcra:0x00000001 event:0050 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_G25 : LSU0 unaligned store flushes (4k boundary)
mmcr0:0x0400C000 mmcr1:0x40C00000828A028A mmcra:0x00000001 event:0051 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_G25 : A conditionalbransh was predicted
mmcr0:0x0400C000 mmcr1:0x40C00000828A028A mmcra:0x00000001 event:0052 counters:2 um:zero minimum:1000 name:PM_EINST_CMPL_G25 : Number of Eligible instrcutions completed
mmcr0:0x0400C000 mmcr1:0x40C00000828A028A mmcra:0x00000001 event:0053 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_G25 : Flush initiated by LSU
mmcr0:0x0400C000 mmcr1:0x40C00000828A028A mmcra:0x00000001 event:0054 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G25 : PPC Instructions completed
mmcr0:0x0400C000 mmcr1:0x40C00000828A028A mmcra:0x00000001 event:0055 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G25 : Proc cycles gated by run latch

#Group 29 LSU Stalls
mmcr0:0x0400C000 mmcr1:0x4000000002341E36 mmcra:0x00000001 event:0060 counters:0 um:zero minimum:1000 name:PM_EINST_CMPL_G29 : Eligible instructions completed
mmcr0:0x0400C000 mmcr1:0x4000000002341E36 mmcra:0x00000001 event:0061 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_G29 : Completion stall Dcache miss
mmcr0:0x0400C000 mmcr1:0x4000000002341E36 mmcra:0x00000001 event:0062 counters:2 um:zero minimum:1000 name:PM_CYC_G29 : Processor cycles
mmcr0:0x0400C000 mmcr1:0x4000000002341E36 mmcra:0x00000001 event:0063 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_G29 : completion stall, ERAT miss
mmcr0:0x0400C000 mmcr1:0x4000000002341E36 mmcra:0x00000001 event:0064 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G29 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x4000000002341E36 mmcra:0x00000001 event:0065 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G29 : Processor cycles gated by run latch

#Group 43 L1 load and TLB misses
mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 event:0071 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_G43 : Data TLB miss occurred
mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 event:0072 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_G43 : L1 D cache load miss
mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 event:0073 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_G43 : L1 D cache load references
mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 event:0074 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G43 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 event:0075 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G43 : Processor cycles gated by run latch

#Group 44 L1 store and DERAT misses
mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 event:0080 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_G44 : Data loaded from L2
mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 event:0081 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_G44 : Data loaded from L3.5 modified
mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 event:0083 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_G44 : L1 D cache store misses
mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 event:0084 counters:4 um:zero minimum:1000 name:PM_PM_INST_CMPL_G44 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 event:0085 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G44 : Processor cycles gated by the run latch

#group 45 L1 load and SLB misses
mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 event:0090 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_G45 : Data SLB misses
mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 event:0091 counters:1 um:zero minimum:1000 name:PM_ISLB_MISS_G45 : Instruction SLB misses
mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 event:0092 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_G45 : LSU0 L1 D cache load misses
mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 event:0093 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_G45 : LSU1 L1 D cache load misses
mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 event:0094 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G45 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 event:0095 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G45 : Processor cycles gated by the run latch

#Group 46 L1 load references and 4k Data TLB references and misses
mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 event:0090 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_4K_G46 : Data TLB reference for 4K page
mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 event:0091 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_4K_G46 : Data TLB miss for 4K page
mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 event:0092 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_G46 : LSU0 L1 D cache load references
mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 event:0093 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_G46 : LSU1 L1 D cache load references
mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 event:0094 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G46 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 event:0095 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G46 : Processor cycles gated by the run latch

#Group 47 L1 store references and 16M Data TLB references and misses
mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 event:0100 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_G47 : Data TLB reference for 16M page
mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 event:0101 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_G47 : Data TLB miss for 16M page
mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 event:0102 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_G47 : FPU0 executed FRSP or FCONV instructions
mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 event:0103 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_G47 : LSU1 L1 Dcache store references
mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 event:0104 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G47 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 event:0105 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G47 : Processor cycles gated by the run latch

#Group 48 L3 cache and memory data access
mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 event:0110 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_G48 : Data loaded from L3
mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 event:0111 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_G48 : Data loaded from local memory
mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 event:0112 counters:2 um:zero minimum:1000 name:PM_FLUSH_G48 : Flushes
mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 event:0113 counters:3 um:zero minimum:1000 name:PM_EINST_CMPL_G48 : Eligible instructions that completed
mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 event:0114 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G48 : PPC instructiions completed
mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 event:0115 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G48 : Processor cycles gated by the run latch

#Group 49 L3 cacahe and memory data access
mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 event:0120 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_G49 : Data loaded from L3
mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 event:0121 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_G49 : Data loaded from Memory
mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 event:0122 counters:2 um:zero minimum:1000 name:PM_EINST_CMPL_G49 : Eligible instructions completed
mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 event:0123 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_G49 : Data loaded from remote memory
mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 event:0124 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G49 : PPC instructions compled
mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 event:0125 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G49 : Processor cycles gated by run latch

#Group 50 L2 cache data access
mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 event:0130 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_G50 : Data loaded from L2.5 shared
mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 event:0131 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_G50 : Data loaded from L2.5 modified
mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 event:0132 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_G50 : Data loaded from L2.75 shared
mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 event:0133 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_G50 : Data loaded from L2.75 modified
mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 event:0134 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G50 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 event:0135 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G50 : Processor cycles gated by run latch

#Group 51 L3 cache data access
mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 event:0140 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_G51 : Data loaded from L3.5 shared
mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 event:0141 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_G51 : Data loaded from L3.5 modified
mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 event:0142 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L375_SHR_G51 : Data loaded from L3.75 shared
mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 event:0143 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L375_MOD_G51 : Data loaded from L3.75 modified
mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 event:0144 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G51 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 event:0145 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G51 : Processor cycles gated by run latch

#Group 52 Instruction source information
mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 event:0150 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L3_G52 : Instruction fetrched from L3
mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 event:0151 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_G52 : Instruction fetched from L1
mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 event:0152 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_G52 : Instructions fetched from prefetch
mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 event:0153 counters:3 um:zero minimum:1000 name:PM_INST_FROM_RMEM_G52 : Instruction fetched from remote memory
mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 event:0154 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G52 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 event:0155 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G52 : Processor Cycles gated by the run latch

#Group 54 L2 instruction source information
mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 event:0160 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L25_SHR_G54 : Instruction fetched from L2.5 shared
mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 event:0161 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_G54 : Instruction fetched from L2.5 modified
mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 event:0162 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L275_SHR_G54 : Instruction fetched from L2.75 shared
mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 event:0163 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L275_MOD_G54 : Instruction fetched from L2.75 modified
mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 event:0164 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G54 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 event:0165 counters:5 um:zero minimum:1000 name:PM_RUN_CYC_G54 : Processor cycles gated by the run latch

#Group 55 L3 instruction source information
mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 event:0170 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L35_SHR_G55 : Instruction fetched from L3.5 shared
mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 event:0171 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L35_MOD_G55 : Instruction fetched from L3.5 modified
mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 event:0172 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L375_SHR_G55 : Instruction fetched from L3.75 shared
mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 event:0173 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L375_MOD_G55 : Instruction fetched from L3.75 modified
mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 event:0174 counters:4 um:zero minimum:1000 name:PM_INST_CMPL_G55 : PPC instructions completed
mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 event:0175 counters:4 um:zero minimum:1000 name:PM_RUN_CYC_G55 : Processor cycles gated by the run latch
