# ppc64 POWER4 events
#
#  Within each group the event names must be unique.  Each event in a group is assigned to a unique counter.  The groups are from the groups defined in the
#  power 4 manual.
#
#  Only events within the same group can be selected simultaneously
#  Each event is given a unique event number.  The event number is used by the Oprofile code
#  to resolve event names for the postprocessing.  This is done to preserve compatibility 
#  with the rest of the Oprofile code.  The event number format group_num followed by the
#  counter number for the event within the group.  The event number must be between 0 and 255.

#Group Default
mmcr0:0x00000D0E  mmcr1:0x000000004A5675AC mmcra:0x00022000 event:0001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles

#Group 1 pm_slice0
mmcr0:0x00000D0E mmcr1:0x000000004A5675AC mmcra:0x00022000 event:0010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GR1 : (Group 1 pm_slice0) Processor Cycles gated by the run latch
mmcr0:0x00000D0E  mmcr1:0x000000004A5675AC mmcra:0x00022000 event:0011 counters:1 um:zero minimum:10000 name:PM_CYC_GR1 : (Group 1 pm_slice0) Processor Cycles
mmcr0:0x00000D0E  mmcr1:0x000000004A5675AC mmcra:0x00022000 event:0013counters:3 um:zero minimum:5000 name:PM_INST_CMPL_GR1 : (Group 1 pm_slice0) Number of eligible instructions that completed

#Group 2 pm_basic
mmcr0:0x0000090E mmcr1:0x1003400045F29420 mmcra:0x00002000 event:0020 counters:0 um:zero minimum:5000 name:PM_INST_CMPL_GR2 : (Group 2 pm_basic) Instrucitons completed
mmcr0:0x0000090E mmcr1:0x1003400045F29420 mmcra:0x00002000 event:0021 counters:1 um:zero minimum:5000 name:PM_CYC_GR2 : (Group 2 pm_basic) Processor cycles
mmcr0:0x0000090E mmcr1:0x1003400045F29420 mmcra:0x00002000 event:0022 counters:2 um:zero minimum:5000 name:PM_LD_MISS_1_GR2 : (Group 2 pm_basic) Total DL1 load references that miss the DL1
mmcr0:0x0000090E mmcr1:0x1003400045F29420 mmcra:0x00002000 event:0023 counters:3 um:zero minimum:5000 name:PM_DC_INV_L2_GR2 : (Group 2 pm_basic) A Dcache invalidated was received from the L2 because a line in L2 was castout
mmcr0:0x0000090E mmcr1:0x1003400045F29420 mmcra:0x00002000 event:0024 counters:4 um:zero minimum:5000 name:PM_INST_DISP_GR2 : (Group 2 pm_basic) The ISU sends the number of instructions dispatched
mmcr0:0x0000090E mmcr1:0x1003400045F29420 mmcra:0x00002000 event:0025 counters:5 um:zero minimum:5000 name:PM_INST_CMPL_GR2 : (Group 2 pm_basic) Number of ELigible Instructions that completed
mmcr0:0x0000090E mmcr1:0x1003400045F29420 mmcra:0x00002000 event:0026 counters:6 um:zero minimum:5000 name:PM_ST_REF_L1_GR2 : (Group 2 pm_basic) Total DL1 store references
mmcr0:0x0000090E mmcr1:0x1003400045F29420 mmcra:0x00002000 event:0027 counters:7 um:zero minimum:5000 name:PM_LD_REF_L1_GR2 : (Group 2 pm_basic) Total DL1 load references


#Group 3 pm_lsource
mmcr0:0x00000E1C mmcr1:0x0010C000739CE738 mmcra:0x00002000 event:0030 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GR3 : (Group 3 pm_lsource) Data loaded from L3 due to a demand load
mmcr0:0x00000E1C mmcr1:0x0010C000739CE738 mmcra:0x80002000 event:0031 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GR3 : (Group 3 pm_lsource) Data loaded from MEM due to a demand load
mmcr0:0x00000E1C mmcr1:0x0010C000739CE738 mmcra:0x00002000 event:0032 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3.5_GR3 : (Group 3 pm_lsource) Data loaded from L3 of another MCM due to a demand load
mmcr0:0x00000E1C mmcr1:0x0010C000739CE738 mmcra:0x00002000 event:0033 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GR3 : (Group 3 pm_lsource) Data loaded from L2 due to a demand load
mmcr0:0x00000E1C mmcr1:0x0010C000739CE738 mmcra:0x00002000 event:0034 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GR3 : (Group 3 pm_lsource) Data reloaded with shared (T) data from the L2 of a chip on this MCM due to a demand load
mmcr0:0x00000E1C mmcr1:0x0010C000739CE738 mmcra:0x00002000 event:0035 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GR3 : (Group 3 pm_lsource) Data reloaded with shared (T) data from the another MCM due to a demand load
mmcr0:0x00000E1C mmcr1:0x0010C000739CE738 mmcra:0x00002000 event:0036 counters:6 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GR3 : (Group 3 pm_lsource) Data reloaded with modified (M) data from the another MCM due to a demand load
mmcr0:0x00000E1C mmcr1:0x0010C000739CE738 mmcra:0x00002000 event:0037 counters:7 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GR3 : (Group 3 pm_lsource) Data reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load

#Group 4 pm_lsource2
mmcr0:0x00000938 mmcr1:0x0010C0003B9CE738 mmcra:0x00002000 event:0040 counters:0 um:zero minimum:1000 name:PM_INST_CMPL_GR4 : (Group 4 pm_lsource2) Number of Eligible Instructions that completed
mmcr0:0x00000938 mmcr1:0x0010C0003B9CE738 mmcra:0x00002000 event:0041 counters:0 um:zero minimum:1000 name:PM_L2_DCACHE_RELOAD_VALID_GR4 : (Group 4 pm_lsource2) The data source information is valid
mmcr0:0x00000938 mmcr1:0x0010C0003B9CE738 mmcra:0x00002000 event:0042 counters:0 um:zero minimum:1000 name:PM_CYC_GR4 : (Group 4 pm_lsource2) Processor Cycles
mmcr0:0x00000938 mmcr1:0x0010C0003B9CE738 mmcra:0x00002000 event:0043 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GR4 : (Group 4 pm_lsource2) DL1 was reloaded from the local L2 due to a demand load
mmcr0:0x00000938 mmcr1:0x0010C0003B9CE738 mmcra:0x00002000 event:0044 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SH_GR4 : (Group 4 pm_lsource2) Data reloaded with shared (T) data from the L2 of a chip on this MCM due to a demand load
mmcr0:0x00000938 mmcr1:0x0010C0003B9CE738 mmcra:0x00002000 event:0045 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GR4 : (Group 4 pm_lsource2) Data reloaded with shared (T) data from the another MCM due to a demand load
mmcr0:0x00000938 mmcr1:0x0010C0003B9CE738 mmcra:0x00002000 event:0046 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GR4 : (Group 4 pm_lsource2) Data reloaded with modified (M) data from the another MCM due to a demand load
mmcr0:0x00000938 mmcr1:0x0010C0003B9CE738 mmcra:0x00002000 event:0047 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GR4 : (Group 4 pm_lsource2) Data reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load

#Group 5 pm_lsource3
mmcr0:0x00000E1C mmcr1:0x0010C00073B87724 mmcra:0x00022000 event:0050 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP5 : (Group 5 pm_lsource3) Data loaded from L3
mmcr0:0x00000E1C mmcr1:0x0010C00073B87724 mmcra:0x00022000 event:0051 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP5 : (Group 5 pm_lsource3) Data loaded from memory
mmcr0:0x00000E1C mmcr1:0x0010C00073B87724 mmcra:0x00022000 event:0052 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L35_GRP5 : (Group 5 pm_lsource3) Data loaded from L3 of another MCM
mmcr0:0x00000E1C mmcr1:0x0010C00073B87724 mmcra:0x00022000 event:0053 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP5 : (Group 5 pm_lsource3) Data loaded from L2
mmcr0:0x00000E1C mmcr1:0x0010C00073B87724 mmcra:0x00022000 event:0054 counters:4 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD : (Group 5 pm_lsource3) L1 reloaded data source valid
mmcr0:0x00000E1C mmcr1:0x0010C00073B87724 mmcra:0x00022000 event:0055 counters:5 um:zero minimum:1000 name:PM_CYC : (Group 5 pm_lsource3) Processor Cycles
mmcr0:0x00000E1C mmcr1:0x0010C00073B87724 mmcra:0x00022000 event:0056 counters:6 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD : (Group 5 pm_lsource3) Data loaded from L2 of another MCM
mmcr0:0x00000E1C mmcr1:0x0010C00073B87724 mmcra:0x00022000 event:0057 counters:7 um:zero minimum:1000 name:PM_INST_CMPL : (Group 5 pm_lsource3) Instructions completed

#Group 6 pm_isource
mmcr0:0x00000F1E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0060 counters:0 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP6 : (Group 6 pm_isource) Instruction fetched from memory
mmcr0:0x00000F1E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0061 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_L275_GRP6 : (Group 6 pm_isource) Instruction fetched from L2 of another chip
mmcr0:0x00000F1E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0062 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP6 : (Group 6 pm_isource) Instructions fetched from L2
mmcr0:0x00000F1E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0063 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L35_GRP6 : (Group 6 pm_isource) Instructions fetched from L3 of another module
mmcr0:0x00000F1E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0064 counters:4 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP6 : (Group 6 pm_isource) Instructions fetched from L3
mmcr0:0x00000F1E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0065 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP6 : (Group 6 pm_isource) Instructions fetched from L1
mmcr0:0x00000F1E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0066 counters:6 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP6 : (Group 6 pm_isource) Instructions fetched from prefetch
mmcr0:0x00000F1E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0067 counters:7 um:zero minimum:1000 name:PM_0INST_FETCH_GRP6 : (Group 6 pm_isource) No instructions fetched

#Group 7 pm_isource2
mmcr0:0x0000090E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0070 counters:0 um:zero minimum:1000 name:PM_INST_CMPL_GRP7 : (Group 7 pm_isource) Instructions completed
mmcr0:0x0000090E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0071 counters:1 um:zero minimum:1000 name:PM_CYC_GRP7 : (Group 7 pm_isource) Processor cycles
mmcr0:0x0000090E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0072 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP7 : (Group 7 pm_isource) Instructions fetched from L2
mmcr0:0x0000090E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0073 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L35_GRP7 : (Group 7 pm_isource) Instructions fetched from L3 of another module
mmcr0:0x0000090E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0074 counters:4 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP7 : (Group 7 pm_isource) Instructions fetched from L3
mmcr0:0x0000090E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0075 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP7 : (Group 7 pm_isource) Instructions fetched from L1
mmcr0:0x0000090E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0076 counters:6 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP7 : (Group 7 pm_isource) Instructions fetched from prefetch
mmcr0:0x0000090E mmcr1:0x800000007BDEF7BC mmcra:0x00022000 event:0077 counters:7 um:zero minimum:1000 name:PM_0INST_FETCH_GRP7 : (Group 7 pm_isource) No instructions fetched

#Group 8 pm_isource3
mmcr0:0x00000F1E mmcr1:0x800000007BDEF3A4 mmcra:0x00022000 event:0080 counters:0 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP8 : (Group 8 pm_isource) Instruction fetched from memory
mmcr0:0x00000F1E mmcr1:0x800000007BDEF3A4 mmcra:0x00022000 event:0081 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_L275_GRP8 : (Group 8 pm_isource) Instruction fetched from L2 of another chip
mmcr0:0x00000F1E mmcr1:0x800000007BDEF3A4 mmcra:0x00022000 event:0082 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP8 : (Group 8 pm_isource) Instructions fetched from L2
mmcr0:0x00000F1E mmcr1:0x800000007BDEF3A4 mmcra:0x00022000 event:0083 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L35_GRP8 : (Group 8 pm_isource) Instructions fetched from L3 of another module
mmcr0:0x00000F1E mmcr1:0x800000007BDEF3A4 mmcra:0x00022000 event:0084 counters:4 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP8 : (Group 8 pm_isource) Instructions fetched from L3
mmcr0:0x00000F1E mmcr1:0x800000007BDEF3A4 mmcra:0x00022000 event:0085 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP8 : (Group 8 pm_isource) Instructions fetched from L1
mmcr0:0x00000F1E mmcr1:0x800000007BDEF3A4 mmcra:0x00022000 event:0086 counters:6 um:zero minimum:1000 name:PM_CYC_GRP8 : (Group 8 pm_isource) Processor cycles
mmcr0:0x00000F1E mmcr1:0x800000007BDEF3A4 mmcra:0x00022000 event:0087 counters:7 um:zero minimum:1000 name:PM_INST_CMPL_GRP8 : (Group 8 pm_isource) Instructions completed

#Group 37 pm_xlate1
mmcr0:0x00001028 mmcr1:0x81082000F67E849C mmcra:0x00022000 event:0090 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP37 : (Group 37 pm_xlate1) A TLB miss for an Instruction fetch has occured
mmcr0:0x00001028 mmcr1:0x81082000F67E849C mmcra:0x00022000 event:0091 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP37 : (Group 37 pm_xlate1) A TLB miss for a data fetch has occured
mmcr0:0x00001028 mmcr1:0x81082000F67E849C mmcra:0x00022000 event:0094 counters:4 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP37 : (Group 37 pm_xlate1) Write to the I-ERAT occured.
mmcr0:0x00001028 mmcr1:0x81082000F67E849C mmcra:0x00022000 event:0095 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP37 : (Group 37 pm_xlate1) Requests that miss the Derat are retied until they hit in the ERAT.  
mmcr0:0x00001028 mmcr1:0x81082000F67E849C mmcra:0x00022000 event:0096 counters:6 um:zero minimum:1000 name:PM_INST_CMPL : (Group 37 pm_xlate1) Instructions completed
mmcr0:0x00001028 mmcr1:0x81082000F67E849C mmcra:0x00022000 event:0097 counters:7 um:zero minimum:1000 name:PM_CYC_GRP37 : (Group 37 pm_xlate1)  Processor cycles

#Group 38 pm_slate1
mmcr0:0x0000112A mmcr1:0x81082000D77E849C mmcra:0x00022000 event:0100 counters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP38 : (Group 38 pm_slate1) A SLB miss for an Instruction fetch has occured
mmcr0:0x0000112A mmcr1:0x81082000D77E849C mmcra:0x00022000 event:0101 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP38 : (Group 38 pm_slate1) A DLB miss for a data fetch has occured
mmcr0:0x0000112A mmcr1:0x81082000D77E849C mmcra:0x00022000 event:0104 counters:4 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP38 : (Group 38 pm_xlate1) Write to the I-ERAT occured.
mmcr0:0x0000112A mmcr1:0x81082000D77E849C mmcra:0x00022000 event:0105 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP38 : (Group 38 pm_xlate1) Requests that miss the Derat are retied until they hit in the ERAT.  
mmcr0:0x0000112A mmcr1:0x81082000D77E849C mmcra:0x00022000 event:0106 counters:6 um:zero minimum:1000 name:PM_INST_CMPL_GRP38 : (Group 38 pm_xlate1) Instructions completed
mmcr0:0x0000112A mmcr1:0x81082000D77E849C mmcra:0x00022000 event:0107 counters:7 um:zero minimum:1000 name:PM_CYC_GRP38 : (Group 38 pm_xlate1)  Processor cycles
